1. Field of the Invention
The present invention relates to a semiconductor device and a method for the fabrication thereof, and more particularly to a semiconductor device suitable for use in an analog circuit of the type in which a capacitor comprises polycrystalline silicon layers, especially a switched capacitor circuit, and a method for the fabrication of such a semiconductor device.
2. Description of the Prior Art
Miniaturization (that is, the reduction in size and weight) of semiconductor devices has recently advanced remarkably, resulting in reduction in size of gates created in each element and narrowing of the line width of interconnection and intraconnection wiring or lines. In order to overcome the short channel effect due to extremely narrow width of interconnection and intraconnection lines or wiring, Japanese Patent Application Publication No. 31506/1987 discloses the so-called lightly doped drain or LDD structure in which an insulating layer is formed by CVD (Chemical Vapor Deposition) by utilizing thermal decomposition of tetraethoxysilane (TEOS) and the side walls are defined by an anisotropic dry etching process, thus defining a double-construction source as well as a double-construction drain. In addition, the reduction in line width of the inter- and intraconnections due to miniaturization has caused the increase of resistance value. This results in the delay of signal transmission. In order to overcome this problem, U.S. Pat. No. 4,392,299 discloses a structure in which a metal silicide is deposited over one surface of a polycrystalline wafer to form gates and wiring having low resistances.
However, since in general, an analog circuit includes a relatively large number of resistors and capacitors, when a resistor having a high resistance is formed by a wiring created by the aforementioned lamination of the low resistance polycrystalline silicon and the silicide, there arises a problem that the length of wiring must be large enough. This inevitably leads to increase in the area of the semiconductor chip used.
FIG. 1 is a circuit diagram schematically showing a conventional switched capacitor or SCF, in which each of C1 and C2 comprises a plurality of unit capacitors. Referring to FIGS. 2A to 2I, description will be made of a conventional method for the production of a semiconductor device containing such unit capacitors. First, as shown in FIG. 2A, a field oxide layer 2 is grown over one surface of a semiconductor wafer 1, and then a first polycrystalline silicon layer 3 is formed over the upper or exposed surface of the field oxide layer 2 by, for example, thermal decomposition of SiH.sub.4 gas. Into the first polycrystalline silicon layer 3, there is diffused POCl.sub.3 or the like so that the first polycrystalline silicon layer 3 is doped with phosphorus as impurity in a high concentration, thereby creating a heavy-doped layer H.sub.1. Next, as shown in FIG. 2B, after a photoresist material 8 is coated over both a transistor formation region A and a capacitor formation region B, respectively, the first polycrystalline silicon layer 3 is subjected to patterning by photolithographic and etching processes, to form a gate electrode 3A (H.sub.1) and a lower capacitor electrode 3B (H.sub.2), respectively (See FIG. 2C). In FIGS. 2A to 2H, reference numeral 10 indicates a gate oxide layer.
Thereafter, as shown in FIG. 2D, by utilizing, for example, a thermal oxidation or CVD process, an insulating interlayer 4 is formed over the exposed surfaces of the heavy-doped layers H.sub.1. Next a second polycrystalline silicon layer 5 is formed over the exposed surfaces of the insulating layer 4 (See FIG. 2E). The second polycrystalline silicon layer 5 is doped with phosphorus to a high concentration by a process similar to that employed in the formation of the first polycrystalline silicon layer 3. The second layer 5 has a low resistance and, hence, it is called a heavy doped layer H.sub.2 (See FIG. 2F). Thereafter, a photoresist land 9 is formed over the heavy-doped layer 5 as shown in FIG. 2G, and then the heavy-doped layer 5 is patterned by, for example, a photolithographic process, to thereby form a required pattern as shown in FIG. 2H.
FIGS. 3A to 3I show schematic sectional views showing semiconductors, respectively, in respective steps of a conventional method for fabricating a semiconductor device in which process the second polycrystalline silicon layer 5 is patterned first and then the first polycrystalline silicon layer 3 is patterned. In the above described fabrication methods, the first polycrystalline silicon layer contains or is doped with impurities in high concentration in order to decrease resistances of the gate electrode and a poly-resistor (not shown). As a result, crystal grains grow during the doping or heat-treatment step of the lower electrode of the capacitor formed with the first polycrystalline silicon layer, resulting in that the layer surface becomes uneven. In the case of a unit capacitor formed on the uneven surface of the polycrystalline silicon layer 3, the degree of precision or specific ratio, that is, the ratio of capacitance of the capacitor C.sub.2 to that of the capacitor C.sub.1 shown in FIG. 1, is decreased. For instance, such degree of precision determines the characteristics not only of an integrator but also SCF. Furthermore, when SCFs include capacitors with low degrees of precision or specific capacitance ratios, their characteristics fluctuate one from another considerably.
Furthermore, the gate oxide layers or insulating interlayers suffer from decrease in their breakdown voltage due to contamination with impurities from metal silicides and the like. This raises a problem that when the gate oxide layers and the insulating interlayers of the capacitors are formed after the formation of the metal silicide layer, reliability is deteriorated. In addition, there has been a demand for forming the gate oxide layer and the insulating interlayer of a capacitor independently of each other so that there can be used different oxidation processes suitable for the gate oxide layer and insulating interlayer, perceptively.